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Advanced Packaging
Enabling the Post Moore Era Eelco Bergman Sr. Director, Business Development September 12, 2019
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Contents • ASE Introduction • Semiconductor Market • Heterogeneous Integration Drivers • Advanced Packaging Solutions • Challenges & Opportunities • Summary
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ASE at a Glance Established 1984, production commenced at flagship factory in Kaohsiung, Taiwan Achieved global leadership in IC Assembly, Test & Materials (ATM) in 2003 & maintained #1 OSAT position since Completed acquisition of Universal Scientific Industrial Co. (USI) to expand DMS/EMS/ODM module & system manufacturing capability Completed acquisition of SPIL, Ltd. to expand IC assembly & test manufacturing capability Operating at 19 facilities worldwide, serving multiple markets, applications & geographies > 90K employees: Global team comprises operations, engineering, R&D, sales & marketing ASE Technology Holding overall revenue (pro forma) of $13.2B in 2018
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ASE Organization ASE Technology Holding, Co. Est. 2018
ASE
SPIL
USI
IC Assembly, Test & Materials Est. 1984
IC Assembly & Test
DMS/EMS/ODM
Est. 1984
Est. 1976
2018 Revenue: $5.3B
2018 Revenue: $2.9B
2018 Revenue: $5.0B
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ASE in the Electronics Value Chain Bridging OSAT and EMS
Semiconductor Design •IDM •Fabless •OEM
Wafer Fabrication
Packaging & Test
SiP Module
PCBA / System
•IDM •Wafer Foundry
•IDM •OSAT •Wafer Foundry
•OSAT •ODM •DMS / EMS
•DMS / EMS •ODM •IDM
ASE Group Service
Engineering Test
Bumping Assembly Wafer Sort Component Test Substrate
Module Design Module Assembly Module Test Component Sourcing FAE Support
System Design System Assembly System Test Software Development Logistics Product Marketing Sales & Support 5
Semiconductor Revenue vs. Process Generation Technology Node
Revenue US $
10 um
10000nm (10um)
400 B
3 um 1 um
1000nm (1 um)
300 B
0.35 um 90 nm
100nm
200 B 28 nm
10nm
100 B
7 nm 3 nm
1 nm 1970
1980
1990
2000
2010
2020
2030 6
Chip & System Integration 10 um
DIP
SiP: Package Integration QFP
Technology Node
3 um 1 um
BGA 0.8 um
FC BGA
2.5D
0.35 um
SoC: Chip Integration 1980
1990
2000
28 nm
2010
7 nm
3 nm
2020
2030
Heterogeneous Integration
Complexity
1970
90 nm
Module: System Integration
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Role and Value of Semiconductor Packaging Increasing Technology Node
Packaging Revenue US $ 500 um 250 um
PCB/Substrate 100 um
50 X
60 B
50 um
10 um
10000nm (10um)
10 um
3 um
50 B 5 um 40 B
1 um
1000nm (1 um)
0.35 um 90 nm
100nm
1600 X
Value of Packaging
28 nm
30 B
20 B 7 nm
10nm CMOS
3 nm
10 B
1 nm 1970
1980
1990
2000
2010
2020
2030 8
Drivers for Heterogeneous Integration • Moore’s law slowing • Exponential rise in chip development costs
Chip Development Cost
• Decreasing number of leading edge fabs • SoC scaling cost barriers • Increasing cost per transistor on advanced node • Increasing SoC die size – wafer yield/die cost impact
• SoC scaling technology barriers • Integration challenges for logic, analog and memory
Source: IBS
• Reduced availability of IP for advanced nodes
• Opportunity to leverage mature process nodes for analog and other IP blocks • Performance and cost optimized • Design re-use / increased flexibility • Faster time to market
• Virtual SoC
Source: Intel 9
Advanced Integration Solutions - Foundry • WLSI – Wafer Level System Integration • • • • • • • •
InFO (Integrated FanOut) InFO_PoP (FO Pkg on Pkg) InFO_AiP (FO with Antenna in Pkg) MUST (Multi-Stack) InFo_oS (FO on Substrate) InFO_MS (FO with Memory on Substrate) InFO_UHD (FO Ultra High Density) CoWoS (Chip on Wafer on Substrate- 2.5D)
• Applications Mobile AP, RF FEM, Baseband, etc.
High Performance Mobile, Network, AI/HPC, etc. Source: WikiChip (Semicon, July 2019) 10
Advanced Integration Solutions - IDM • HPC Packaging Toolbox • EMIB: Embedded interconnect bridge in organic substrate • Foveros: Integration on TSV interposer • Co-EMIB: Integration of multiple Foveros structures and memory/IP chiplets using EMIB • ODI (Omni Directional Interconnect): Integration on reduced size interposer enabling direct vertical interconnect to top die for power delivery
Source: Intel/EE Times (07.09.19) 11
Die Level Interconnects
Advanced Integration Solutions - OSAT • Interconnection through post-fab RDL (FanOut) • Line/space: > 2um
100,000’s
10,000’s
1,000’s
• Interconnection through organic substrate • Line/space: > 10um
2.5D TSV • Interconnection through silicon interposer • Line/space: > 0.4um
FanOut FOCoS
PoP, SiP MCM
25/25
15/15
10/10
5/5
2/2
1/1
0.5/0.5
Line / Space (um) 12
MCM • • • • • •
Die partition or multi device integration on organic substrate High performance SoC and IP die (i.e. SERDES) integration Multi fab/process node device combinations Low to medium interconnect density: 100’s-1000’s Separation of digital/analog blocks Benefits • • • •
Enables IP reuse with advanced wafer node devices Reduced SoC design and validation time Enable multiple sources for ‘standard’ IP blocks / devices Smaller SoC die size – increased yield
• Lower bump/die stress – increased reliability
SoC + 16 chiplets 60um die to die spacing min 13
FanOut / FOCoS • Homogeneous partition • Yield & cost optimization • Scalable integration
• Heterogenous die partition
28nm
• Process and performance optimization
16nm
Fan Out Compound Die
• Medium to high interconnect density
Fan Out Hybrid BGA Package
• 1000’s to 10,000’s
• Separation of digital/analog/memory • Benefits • • • •
Die size, yield and cost optimization Process node / functionality optimization Short, high density interconnect Increased reliability
2/2 µm Lines/Spaces
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2.5D TSV • Homogeneous partition • Yield & cost optimization • Scalable integration
• Heterogenous die integration • SoC, HBM2 & SerDes
HBM2 stack
SoC
HBM2 stack
• High interconnect density • 10,000’s to 100,000 • 40um microbump pitch
• Benefits • • • • •
Silicon interconnect performance High bandwidth interface enablement Reduced power Si on Si first level interconnect System board size reduction 15
Challenges & Opportunities • Supply chain • Chiplet ecosystem enablement • • •
IP chiplet type/functionality development roadmap and priorities Pin out/interface standards (by chiplet type/function) where possible (eg. JEDEC HMB ‘chiplet’ spec) KGD performance and reliability criteria definition
• Business model definition and development •
Who is selling what to whom? What are associated liability limitations?
• Design & Simulation • Co-design flow definition and optimization •
Development of packaging PDK for various package integration solutions
• Import and integration capability of multi-device GDS into package design tool •
Chiplet representation for EDA – ODSA CDX (Chiplet Design Exchange)
• Multi-physics simulation tools for multi-device integration design validation •
SiP and virtual SoC system simulation
• DFT/Test • Chiplet KGD testing standards & criteria • Debug and final test of multi device SiP or virtual SoC •
Failure isolation and identification
• ATE vs. SLT 16
Summary Convergence of Device and System Integration
Die Disaggregaton
Integration for Performance & Cost PoP / MCM / FOCoS / 2.5D System-in-Package (SiP)
System OEM Driven PCBA Miniaturization
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Thank You w w w. a s e g l o b a l . c o m
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